The present invention relates generally to information handling systems and more particularly to an improved methodology for referencing information in registers of computer processing units.
High performance superscalar computer processors use a technique known as xe2x80x9cregister renamingxe2x80x9d to facilitate out-of-order instruction execution. In general, register renaming refers to a method by which processor registers may be shared. For example, if a first program requires the use of a specific register, and a second program also requires the use of that same register while the register is still being used by the first program, the processor will redefine one of its unused registers as a second copy of the specific register, and the processor will track and manage the specific register and the renamed register relative to the information contained in the registers and the associated instructions.
Every computer program consists of a sequence of small atomic actions called instructions which collectively, and in sequence, comprise the program. Though, in the program""s object file, these instructions exist in a formal sequence, when executed on a superscalar computer processor, the program instructions may be executed out of order by the processor, provided the required dependencies inside the program are not violated. For example, if instruction B references a particular register, and instruction A, which precedes B in program flow, also writes to that register, B must wait for A to complete. This ordering requirement is referred to as a dependency. The fewer the dependencies, the faster the instructions can be delivered to the execution units. Dependencies can also arise due to implementation decisions which have the same detrimental effect on performance.
A problem arises when instructions are executed simultaneously and/or out-of-order. It is no longer sufficient to name a result in this system by the number of the destination register since multiple results may be concurrently outstanding for that register, and there is a strict ordering between the results as dictated by the program sequence. To manage that problem, superscalar processors typically rename the source and destination operands of each program instruction with a code corresponding to an implementation level register (referred to as the xe2x80x9crenamed registerxe2x80x9d) that can be used to correctly order the values as they are produced by the various parts of the execution stage.
To date, processors have implemented register renaming by assigning an alias code to each operand on the basis of the register identifier and without regard to the portion of the bits of that register which are actually accessed by the instruction. That practice reduces the availability of the renaming registers for other instructions which, in turn, causes a performance problem when subsequent instructions use entirely disjointed portions of a single data register.
Processors architecturally deal with more than one size of data values such as 8, 16, 32 and 64-bit integer operations. For example, the typical RISC (Reduced Instruction Set Computer) processors, such as the PowerPC processor, was introduced as 32-bit architectures and later extended to 64-bits. In this case, the upper and lower 32-bit halves of the 64-bit register are not equally accessible. Existing applications written for the 32-bit processors must still run on the 64-bit processors. When renaming takes place on the full register (64-bits), half of the renaming register bits are wasted when running 32-bit programs or when using 32 or less bits for data values. Full register renaming thus results in unnecessary wastage of register space and this, in turn, results in significant slow-down in program execution when code using 8, 16 or 32 bits of data values, and instruction execution has to be stalled due to an unavailability of rename registers.
Accordingly, there is a need for an enhanced method and processing apparatus which is able to provide increased register efficiencies and improved processor performance.
A method and apparatus is provided for sectoring processor registers and renaming the resulting sectored registers individually. In one embodiment, the register file is divided into sectors such that the smallest accessible unit for an instruction set in each register can be uniquely addressed and renamed. Since most register data values do not utilize all the bits of a given register, such bits that form a register sector can then be utilized to provide additional registers for renaming.